1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# |
13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38#
|
27# Authors: Steve Reinhardt
|
39# Authors: Andreas Hansson |
40
|
29import m5
|
41from m5.objects import *
|
31m5.util.addToPath('../configs/common')
32from Caches import *
|
42from base_config import * |
43
|
34cpu = DerivO3CPU(cpu_id=0)
35cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
36 L1Cache(size = '256kB'),
37 L2Cache(size = '2MB'))
38# @todo Note that the L2 latency here is unmodified and 2 cycles,
39# should set hit latency and response latency to 20 cycles as for
40# other scripts
41cpu.clock = '2GHz'
42
43system = System(cpu = cpu,
44 physmem = DDR3_1600_x64(),
45 membus = CoherentBus(),
46 mem_mode = "timing")
47system.clock = '1GHz'
48system.system_port = system.membus.slave
49system.physmem.port = system.membus.master
50# create the interrupt controller
51cpu.createInterruptController()
52cpu.connectAllPorts(system.membus)
53
54root = Root(full_system = False, system = system)
|
44root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, 45 cpu_class=DerivO3CPU).create_root() |
|