1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32
33class MyCache(BaseCache):
34 assoc = 2
35 block_size = 64
36 hit_latency = 2
37 response_latency = 2
38 mshrs = 10
39 tgts_per_mshr = 5
40
41class MyL1Cache(MyCache):
42 is_top_level = True
43 tgts_per_mshr = 20
44
45cpu = DerivO3CPU(cpu_id=0)
46cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
47 MyL1Cache(size = '256kB'),
48 MyCache(size = '2MB'))
49# @todo Note that the L2 latency here is unmodified and 2 cycles,
50# should set hit latency and response latency to 20 cycles as for
51# other scripts
52cpu.clock = '2GHz'
53
54system = System(cpu = cpu,
55 physmem = SimpleMemory(),
56 membus = CoherentBus())
57system.system_port = system.membus.slave
58system.physmem.port = system.membus.master
59# create the interrupt controller
60cpu.createInterruptController()
61cpu.connectAllPorts(system.membus)
62
63root = Root(full_system = False, system = system)