1# Copyright (c) 2013, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 34 unchanged lines hidden (view full) --- 43from base_config import * 44from arm_generic import * 45from common.O3_ARM_v7a import O3_ARM_v7a_3 46 47# If we are running ARM regressions, use a more sensible CPU 48# configuration. This makes the results more meaningful, and also 49# increases the coverage of the regressions. 50if buildEnv['TARGET_ISA'] == "arm": |
51 root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8, |
52 cpu_class=O3_ARM_v7a_3, 53 num_threads=2).create_root() 54else: |
55 root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8, |
56 cpu_class=DerivO3CPU, 57 num_threads=2).create_root() |