o3-timing-mp.py (9790:ccc428657233) | o3-timing-mp.py (9792:c02004c2cc5b) |
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1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 10 unchanged lines hidden (view full) --- 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# | 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright --- 10 unchanged lines hidden (view full) --- 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# |
27# Authors: Ron Dreslinski | 39# Authors: Andreas Hansson |
28 | 40 |
29import m5 | |
30from m5.objects import * | 41from m5.objects import * |
31m5.util.addToPath('../configs/common') 32from Caches import * | 42from base_config import * |
33 34nb_cores = 4 | 43 44nb_cores = 4 |
35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, 39 physmem = DDR3_1600_x64(), 40 membus = CoherentBus(), 41 mem_mode = "timing") 42system.clock = '1GHz' 43 44# l2cache & bus 45system.toL2Bus = CoherentBus(clock = '2GHz') 46system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 47system.l2c.cpu_side = system.toL2Bus.master 48 49# connect l2c to membus 50system.l2c.mem_side = system.membus.slave 51 52# add L1 caches 53for cpu in cpus: 54 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), 55 L1Cache(size = '32kB', assoc = 4)) 56 # create the interrupt controller 57 cpu.createInterruptController() 58 # connect cpu level-1 caches to shared level-2 cache 59 cpu.connectAllPorts(system.toL2Bus, system.membus) 60 cpu.clock = '2GHz' 61 62# connect memory to membus 63system.physmem.port = system.membus.master 64 65# connect system port to membus 66system.system_port = system.membus.slave 67 68# ----------------------- 69# run simulation 70# ----------------------- 71 72root = Root( full_system = False, system = system ) 73root.system.mem_mode = 'timing' 74#root.trace.flags="Bus Cache" 75#root.trace.flags = "BusAddrRanges" | 45root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64, 46 cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root() |