o3-timing-mp.py (9381:ffec48040ac1) | o3-timing-mp.py (9489:172dbcb74a0e) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34nb_cores = 4 35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34nb_cores = 4 35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, |
39 physmem = SimpleDRAM(), | 39 physmem = SimpleDDR3(), |
40 membus = CoherentBus(), 41 mem_mode = "timing") 42 43# l2cache & bus 44system.toL2Bus = CoherentBus(clock = '2GHz') 45system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 46system.l2c.cpu_side = system.toL2Bus.master 47 --- 27 unchanged lines hidden --- | 40 membus = CoherentBus(), 41 mem_mode = "timing") 42 43# l2cache & bus 44system.toL2Bus = CoherentBus(clock = '2GHz') 45system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 46system.l2c.cpu_side = system.toL2Bus.master 47 --- 27 unchanged lines hidden --- |