| o3-timing-mp.py (9311:227d19399b51) | o3-timing-mp.py (9315:2e00867b5001) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34nb_cores = 4 35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus()) 39 40# l2cache & bus 41system.toL2Bus = CoherentBus(clock = '2GHz') | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34nb_cores = 4 35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus()) 39 40# l2cache & bus 41system.toL2Bus = CoherentBus(clock = '2GHz') |
| 42system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) | 42system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) |
| 43system.l2c.cpu_side = system.toL2Bus.master 44 45# connect l2c to membus 46system.l2c.mem_side = system.membus.slave 47 48# add L1 caches 49for cpu in cpus: | 43system.l2c.cpu_side = system.toL2Bus.master 44 45# connect l2c to membus 46system.l2c.mem_side = system.membus.slave 47 48# add L1 caches 49for cpu in cpus: |
| 50 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 51 L1(size = '32kB', assoc = 4)) | 50 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), 51 L1Cache(size = '32kB', assoc = 4)) |
| 52 # create the interrupt controller 53 cpu.createInterruptController() 54 # connect cpu level-1 caches to shared level-2 cache 55 cpu.connectAllPorts(system.toL2Bus, system.membus) 56 cpu.clock = '2GHz' 57 58# connect memory to membus 59system.physmem.port = system.membus.master --- 12 unchanged lines hidden --- | 52 # create the interrupt controller 53 cpu.createInterruptController() 54 # connect cpu level-1 caches to shared level-2 cache 55 cpu.connectAllPorts(system.toL2Bus, system.membus) 56 cpu.clock = '2GHz' 57 58# connect memory to membus 59system.physmem.port = system.membus.master --- 12 unchanged lines hidden --- |