| o3-timing-mp.py (9310:aa7bf10e822a) | o3-timing-mp.py (9311:227d19399b51) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34nb_cores = 4 35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34nb_cores = 4 35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated |
| 38system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) | 38system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus()) |
| 39 40# l2cache & bus 41system.toL2Bus = CoherentBus(clock = '2GHz') 42system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) 43system.l2c.cpu_side = system.toL2Bus.master 44 45# connect l2c to membus 46system.l2c.mem_side = system.membus.slave --- 25 unchanged lines hidden --- | 39 40# l2cache & bus 41system.toL2Bus = CoherentBus(clock = '2GHz') 42system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) 43system.l2c.cpu_side = system.toL2Bus.master 44 45# connect l2c to membus 46system.l2c.mem_side = system.membus.slave --- 25 unchanged lines hidden --- |