o3-timing-mp.py (9288:3d6da8559605) o3-timing-mp.py (9310:aa7bf10e822a)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 15 unchanged lines hidden (view full) ---

24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
32
33
33# --------------------
34# Base L1 Cache
35# ====================
36
37class L1(BaseCache):
38 hit_latency = 2
39 response_latency = 2
40 block_size = 64
41 mshrs = 4
42 tgts_per_mshr = 20
43 is_top_level = True
44
45# ----------------------
46# Base L2 Cache
47# ----------------------
48
49class L2(BaseCache):
50 block_size = 64
51 hit_latency = 20
52 response_latency = 20
53 mshrs = 92
54 tgts_per_mshr = 16
55 write_buffers = 8
56
57nb_cores = 4
58cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
59
60# system simulated
61system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
62
63# l2cache & bus
64system.toL2Bus = CoherentBus(clock = '2GHz')

--- 30 unchanged lines hidden --- 		34nb_cores = 4
35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37# system simulated
38system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
39
40# l2cache & bus
41system.toL2Bus = CoherentBus(clock = '2GHz')

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