o3-timing-mp.py (8931:7a1dfb191e3f) o3-timing-mp.py (9036:6385cf85bf12)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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51 mshrs = 92
52 tgts_per_mshr = 16
53 write_buffers = 8
54
55nb_cores = 4
56cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
57
58# system simulated
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 42 unchanged lines hidden (view full) ---

51 mshrs = 92
52 tgts_per_mshr = 16
53 write_buffers = 8
54
55nb_cores = 4
56cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
57
58# system simulated
59system = System(cpu = cpus, physmem = SimpleMemory(), membus = Bus())
59system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
60
61# l2cache & bus
60
61# l2cache & bus
62system.toL2Bus = Bus()
62system.toL2Bus = CoherentBus()
63system.l2c = L2(size='4MB', assoc=8)
64system.l2c.cpu_side = system.toL2Bus.master
65
66# connect l2c to membus
67system.l2c.mem_side = system.membus.slave
68
69# add L1 caches
70for cpu in cpus:

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63system.l2c = L2(size='4MB', assoc=8)
64system.l2c.cpu_side = system.toL2Bus.master
65
66# connect l2c to membus
67system.l2c.mem_side = system.membus.slave
68
69# add L1 caches
70for cpu in cpus:

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