o3-timing-mp.py (8833:2870638642bd) | o3-timing-mp.py (8839:eeb293859255) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 48 unchanged lines hidden (view full) --- 57 58# system simulated 59system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 60Bus()) 61 62# l2cache & bus 63system.toL2Bus = Bus() 64system.l2c = L2(size='4MB', assoc=8) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 48 unchanged lines hidden (view full) --- 57 58# system simulated 59system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 60Bus()) 61 62# l2cache & bus 63system.toL2Bus = Bus() 64system.l2c = L2(size='4MB', assoc=8) |
65system.l2c.cpu_side = system.toL2Bus.port | 65system.l2c.cpu_side = system.toL2Bus.master |
66 67# connect l2c to membus | 66 67# connect l2c to membus |
68system.l2c.mem_side = system.membus.port | 68system.l2c.mem_side = system.membus.slave |
69 70# add L1 caches 71for cpu in cpus: 72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) 74 # connect cpu level-1 caches to shared level-2 cache 75 cpu.connectAllPorts(system.toL2Bus, system.membus) 76 cpu.clock = '2GHz' 77 78# connect memory to membus | 69 70# add L1 caches 71for cpu in cpus: 72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) 74 # connect cpu level-1 caches to shared level-2 cache 75 cpu.connectAllPorts(system.toL2Bus, system.membus) 76 cpu.clock = '2GHz' 77 78# connect memory to membus |
79system.physmem.port = system.membus.port | 79system.physmem.port = system.membus.master |
80 81# connect system port to membus | 80 81# connect system port to membus |
82system.system_port = system.membus.port | 82system.system_port = system.membus.slave |
83 84# ----------------------- 85# run simulation 86# ----------------------- 87 88root = Root( full_system = False, system = system ) 89root.system.mem_mode = 'timing' 90#root.trace.flags="Bus Cache" 91#root.trace.flags = "BusAddrRanges" | 83 84# ----------------------- 85# run simulation 86# ----------------------- 87 88root = Root( full_system = False, system = system ) 89root.system.mem_mode = 'timing' 90#root.trace.flags="Bus Cache" 91#root.trace.flags = "BusAddrRanges" |