| o3-timing-mp.py (6978:ab05e20dc4a7) | o3-timing-mp.py (7876:189b9b258779) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 58 unchanged lines hidden (view full) --- 67# connect l2c to membus 68system.l2c.mem_side = system.membus.port 69 70# add L1 caches 71for cpu in cpus: 72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) 74 # connect cpu level-1 caches to shared level-2 cache | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 58 unchanged lines hidden (view full) --- 67# connect l2c to membus 68system.l2c.mem_side = system.membus.port 69 70# add L1 caches 71for cpu in cpus: 72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) 74 # connect cpu level-1 caches to shared level-2 cache |
| 75 cpu.connectMemPorts(system.toL2Bus) | 75 cpu.connectAllPorts(system.toL2Bus, system.membus) |
| 76 cpu.clock = '2GHz' 77 78# connect memory to membus 79system.physmem.port = system.membus.port 80 81 82# ----------------------- 83# run simulation 84# ----------------------- 85 86root = Root( system = system ) 87root.system.mem_mode = 'timing' 88#root.trace.flags="Bus Cache" 89#root.trace.flags = "BusAddrRanges" | 76 cpu.clock = '2GHz' 77 78# connect memory to membus 79system.physmem.port = system.membus.port 80 81 82# ----------------------- 83# run simulation 84# ----------------------- 85 86root = Root( system = system ) 87root.system.mem_mode = 'timing' 88#root.trace.flags="Bus Cache" 89#root.trace.flags = "BusAddrRanges" |