o3-timing-mp.py (6654:4c84e771cca7) | o3-timing-mp.py (6978:ab05e20dc4a7) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 48 unchanged lines hidden (view full) --- 57# system simulated 58system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 59Bus()) 60 61# l2cache & bus 62system.toL2Bus = Bus() 63system.l2c = L2(size='4MB', assoc=8) 64system.l2c.cpu_side = system.toL2Bus.port | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 48 unchanged lines hidden (view full) --- 57# system simulated 58system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 59Bus()) 60 61# l2cache & bus 62system.toL2Bus = Bus() 63system.l2c = L2(size='4MB', assoc=8) 64system.l2c.cpu_side = system.toL2Bus.port |
65system.l2c.num_cpus = nb_cores |
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65 66# connect l2c to membus 67system.l2c.mem_side = system.membus.port 68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) --- 16 unchanged lines hidden --- | 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.port 69 70# add L1 caches 71for cpu in cpus: 72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) --- 16 unchanged lines hidden --- |