| o3-timing-mp.py (3223:a2b6fa575c05) | o3-timing-mp.py (3230:e86a03911728) |
|---|---|
| 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 39 unchanged lines hidden (view full) --- 48class L2(BaseCache): 49 block_size = 64 50 latency = 100 51 mshrs = 92 52 tgts_per_mshr = 16 53 write_buffers = 8 54 55nb_cores = 4 | 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 39 unchanged lines hidden (view full) --- 48class L2(BaseCache): 49 block_size = 64 50 latency = 100 51 mshrs = 92 52 tgts_per_mshr = 16 53 write_buffers = 8 54 55nb_cores = 4 |
| 56cpus = [ DerivO3CPU() for i in xrange(nb_cores) ] | 56cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] |
| 57 58# system simulated 59system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 60Bus()) 61 62# l2cache & bus 63system.toL2Bus = Bus() 64system.l2c = L2(size='4MB', assoc=8) --- 15 unchanged lines hidden (view full) --- 80 81 82# ----------------------- 83# run simulation 84# ----------------------- 85 86root = Root( system = system ) 87root.system.mem_mode = 'timing' | 57 58# system simulated 59system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 60Bus()) 61 62# l2cache & bus 63system.toL2Bus = Bus() 64system.l2c = L2(size='4MB', assoc=8) --- 15 unchanged lines hidden (view full) --- 80 81 82# ----------------------- 83# run simulation 84# ----------------------- 85 86root = Root( system = system ) 87root.system.mem_mode = 'timing' |
| 88root.trace.flags="Bus Cache" | 88#root.trace.flags="Bus Cache" |
| 89#root.trace.flags = "BusAddrRanges" | 89#root.trace.flags = "BusAddrRanges" |