o3-timing-mp.py (3200:4b072dcc7a57) o3-timing-mp.py (3223:a2b6fa575c05)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 15 unchanged lines hidden (view full) ---

24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32from FullO3Config import *
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
39 latency = 1
40 block_size = 64

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49class L2(BaseCache):
50 block_size = 64
51 latency = 100
52 mshrs = 92
53 tgts_per_mshr = 16
54 write_buffers = 8
55
56nb_cores = 4
32
33# --------------------
34# Base L1 Cache
35# ====================
36
37class L1(BaseCache):
38 latency = 1
39 block_size = 64

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48class L2(BaseCache):
49 block_size = 64
50 latency = 100
51 mshrs = 92
52 tgts_per_mshr = 16
53 write_buffers = 8
54
55nb_cores = 4
57cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
56cpus = [ DerivO3CPU() for i in xrange(nb_cores) ]
58
59# system simulated
60system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
61Bus())
62
63# l2cache & bus
64system.toL2Bus = Bus()
65system.l2c = L2(size='4MB', assoc=8)

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81
82
83# -----------------------
84# run simulation
85# -----------------------
86
87root = Root( system = system )
88root.system.mem_mode = 'timing'
57
58# system simulated
59system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
60Bus())
61
62# l2cache & bus
63system.toL2Bus = Bus()
64system.l2c = L2(size='4MB', assoc=8)

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80
81
82# -----------------------
83# run simulation
84# -----------------------
85
86root = Root( system = system )
87root.system.mem_mode = 'timing'
89#root.trace.flags="Bus Cache"
88root.trace.flags="Bus Cache"
90#root.trace.flags = "BusAddrRanges"
89#root.trace.flags = "BusAddrRanges"