o3-timing-mp.py (3134:cf578b0dd70d) | o3-timing-mp.py (3200:4b072dcc7a57) |
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1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 40 unchanged lines hidden (view full) --- 49class L2(BaseCache): 50 block_size = 64 51 latency = 100 52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56nb_cores = 4 | 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 40 unchanged lines hidden (view full) --- 49class L2(BaseCache): 50 block_size = 64 51 latency = 100 52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56nb_cores = 4 |
57cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ] | 57cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ] |
58 59# system simulated 60system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 61Bus()) 62 63# l2cache & bus 64system.toL2Bus = Bus() 65system.l2c = L2(size='4MB', assoc=8) --- 15 unchanged lines hidden (view full) --- 81 82 83# ----------------------- 84# run simulation 85# ----------------------- 86 87root = Root( system = system ) 88root.system.mem_mode = 'timing' | 58 59# system simulated 60system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 61Bus()) 62 63# l2cache & bus 64system.toL2Bus = Bus() 65system.l2c = L2(size='4MB', assoc=8) --- 15 unchanged lines hidden (view full) --- 81 82 83# ----------------------- 84# run simulation 85# ----------------------- 86 87root = Root( system = system ) 88root.system.mem_mode = 'timing' |
89root.trace.flags="Bus Cache" | 89#root.trace.flags="Bus Cache" |
90#root.trace.flags = "BusAddrRanges" | 90#root.trace.flags = "BusAddrRanges" |