1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# |
13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38#
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27# Authors: Ron Dreslinski
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39# Authors: Andreas Hansson |
40
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29import m5
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41from m5.objects import *
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31m5.util.addToPath('../configs/common')
32from Caches import *
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42from base_config import * |
43 44nb_cores = 4
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35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37# system simulated
38system = System(cpu = cpus,
39 physmem = DDR3_1600_x64(),
40 membus = CoherentBus(),
41 mem_mode = "timing")
42system.clock = '1GHz'
43
44# l2cache & bus
45system.toL2Bus = CoherentBus(clock = '2GHz')
46system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
47system.l2c.cpu_side = system.toL2Bus.master
48
49# connect l2c to membus
50system.l2c.mem_side = system.membus.slave
51
52# add L1 caches
53for cpu in cpus:
54 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
55 L1Cache(size = '32kB', assoc = 4))
56 # create the interrupt controller
57 cpu.createInterruptController()
58 # connect cpu level-1 caches to shared level-2 cache
59 cpu.connectAllPorts(system.toL2Bus, system.membus)
60 cpu.clock = '2GHz'
61
62# connect memory to membus
63system.physmem.port = system.membus.master
64
65# connect system port to membus
66system.system_port = system.membus.slave
67
68# -----------------------
69# run simulation
70# -----------------------
71
72root = Root( full_system = False, system = system )
73root.system.mem_mode = 'timing'
74#root.trace.flags="Bus Cache"
75#root.trace.flags = "BusAddrRanges"
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45root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64, 46 cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root() |
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