1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32 33# -------------------- 34# Base L1 Cache 35# ==================== 36 37class L1(BaseCache): |
38 hit_latency = 2 39 response_latency = 2 |
40 block_size = 64 41 mshrs = 4 42 tgts_per_mshr = 20 43 is_top_level = True 44 45# ---------------------- 46# Base L2 Cache 47# ---------------------- 48 49class L2(BaseCache): 50 block_size = 64 |
51 hit_latency = 20 52 response_latency = 20 |
53 mshrs = 92 54 tgts_per_mshr = 16 55 write_buffers = 8 56 57nb_cores = 4 58cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 59 60# system simulated 61system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) 62 63# l2cache & bus |
64system.toL2Bus = CoherentBus(clock = '2GHz') 65system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) |
66system.l2c.cpu_side = system.toL2Bus.master 67 68# connect l2c to membus 69system.l2c.mem_side = system.membus.slave 70 71# add L1 caches 72for cpu in cpus: 73 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), --- 21 unchanged lines hidden --- |