1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 57 unchanged lines hidden (view full) --- 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.slave 69 70# add L1 caches 71for cpu in cpus: 72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) |
74 # create the interrupt controller 75 cpu.createInterruptController() |
76 # connect cpu level-1 caches to shared level-2 cache 77 cpu.connectAllPorts(system.toL2Bus, system.membus) 78 cpu.clock = '2GHz' 79 80# connect memory to membus 81system.physmem.port = system.membus.master 82 83# connect system port to membus 84system.system_port = system.membus.slave 85 86# ----------------------- 87# run simulation 88# ----------------------- 89 90root = Root( full_system = False, system = system ) 91root.system.mem_mode = 'timing' 92#root.trace.flags="Bus Cache" 93#root.trace.flags = "BusAddrRanges" |