1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
33
34nb_cores = 4
35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37# system simulated
38system = System(cpu = cpus,
39 physmem = DDR3_1600_x64(),
40 membus = CoherentBus(),
41 mem_mode = "timing")
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
33
34nb_cores = 4
35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37# system simulated
38system = System(cpu = cpus,
39 physmem = DDR3_1600_x64(),
40 membus = CoherentBus(),
41 mem_mode = "timing")
|
42
43# l2cache & bus
44system.toL2Bus = CoherentBus(clock = '2GHz')
45system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
46system.l2c.cpu_side = system.toL2Bus.master
47
48# connect l2c to membus
49system.l2c.mem_side = system.membus.slave
50
51# add L1 caches
52for cpu in cpus:
53 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
54 L1Cache(size = '32kB', assoc = 4))
55 # create the interrupt controller
56 cpu.createInterruptController()
57 # connect cpu level-1 caches to shared level-2 cache
58 cpu.connectAllPorts(system.toL2Bus, system.membus)
59 cpu.clock = '2GHz'
60
61# connect memory to membus
62system.physmem.port = system.membus.master
63
64# connect system port to membus
65system.system_port = system.membus.slave
66
67# -----------------------
68# run simulation
69# -----------------------
70
71root = Root( full_system = False, system = system )
72root.system.mem_mode = 'timing'
73#root.trace.flags="Bus Cache"
74#root.trace.flags = "BusAddrRanges"
| 43
44# l2cache & bus
45system.toL2Bus = CoherentBus(clock = '2GHz')
46system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
47system.l2c.cpu_side = system.toL2Bus.master
48
49# connect l2c to membus
50system.l2c.mem_side = system.membus.slave
51
52# add L1 caches
53for cpu in cpus:
54 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
55 L1Cache(size = '32kB', assoc = 4))
56 # create the interrupt controller
57 cpu.createInterruptController()
58 # connect cpu level-1 caches to shared level-2 cache
59 cpu.connectAllPorts(system.toL2Bus, system.membus)
60 cpu.clock = '2GHz'
61
62# connect memory to membus
63system.physmem.port = system.membus.master
64
65# connect system port to membus
66system.system_port = system.membus.slave
67
68# -----------------------
69# run simulation
70# -----------------------
71
72root = Root( full_system = False, system = system )
73root.system.mem_mode = 'timing'
74#root.trace.flags="Bus Cache"
75#root.trace.flags = "BusAddrRanges"
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