o3-timing-mp.py (9036:6385cf85bf12) | o3-timing-mp.py (9263:066099902102) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32 33# -------------------- 34# Base L1 Cache 35# ==================== 36 37class L1(BaseCache): | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32 33# -------------------- 34# Base L1 Cache 35# ==================== 36 37class L1(BaseCache): |
38 latency = '1ns' | 38 hit_latency = '1ns' 39 response_latency = '1ns' |
39 block_size = 64 40 mshrs = 4 41 tgts_per_mshr = 20 42 is_top_level = True 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64 | 40 block_size = 64 41 mshrs = 4 42 tgts_per_mshr = 20 43 is_top_level = True 44 45# ---------------------- 46# Base L2 Cache 47# ---------------------- 48 49class L2(BaseCache): 50 block_size = 64 |
50 latency = '10ns' | 51 hit_latency = '10ns' 52 response_latency = '10ns' |
51 mshrs = 92 52 tgts_per_mshr = 16 53 write_buffers = 8 54 55nb_cores = 4 56cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 57 58# system simulated --- 34 unchanged lines hidden --- | 53 mshrs = 92 54 tgts_per_mshr = 16 55 write_buffers = 8 56 57nb_cores = 4 58cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 59 60# system simulated --- 34 unchanged lines hidden --- |