1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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66
67# connect l2c to membus
68system.l2c.mem_side = system.membus.slave
69
70# add L1 caches
71for cpu in cpus:
72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
73 L1(size = '32kB', assoc = 4))
74 # connect cpu level-1 caches to shared level-2 cache
75 cpu.connectAllPorts(system.toL2Bus, system.membus)
76 cpu.clock = '2GHz'
77
78# connect memory to membus
79system.physmem.port = system.membus.master
80
81# connect system port to membus
82system.system_port = system.membus.slave
83
84# -----------------------
85# run simulation
86# -----------------------
87
88root = Root( full_system = False, system = system )
89root.system.mem_mode = 'timing'
90#root.trace.flags="Bus Cache"
91#root.trace.flags = "BusAddrRanges"