| o3-timing-mp-ruby.py (8839:eeb293859255) | o3-timing-mp-ruby.py (8876:44f8e7bb7fdf) |
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| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 35 36import ruby_config 37ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 38 39# system simulated 40system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 41 42for cpu in cpus: | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 35 36import ruby_config 37ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 38 39# system simulated 40system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 41 42for cpu in cpus: |
| 43 # create the interrupt controller 44 cpu.createInterruptController() |
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| 43 cpu.connectAllPorts(system.membus) 44 cpu.clock = '2GHz' 45 46# connect memory to membus 47system.physmem.port = system.membus.master 48 49# Connect the system port for loading of binaries etc 50system.system_port = system.membus.slave 51 52# ----------------------- 53# run simulation 54# ----------------------- 55 56root = Root(full_system = False, system = system) 57root.system.mem_mode = 'timing' | 45 cpu.connectAllPorts(system.membus) 46 cpu.clock = '2GHz' 47 48# connect memory to membus 49system.physmem.port = system.membus.master 50 51# Connect the system port for loading of binaries etc 52system.system_port = system.membus.slave 53 54# ----------------------- 55# run simulation 56# ----------------------- 57 58root = Root(full_system = False, system = system) 59root.system.mem_mode = 'timing' |