1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 32 unchanged lines hidden (view full) --- 41 42for cpu in cpus: 43 cpu.connectAllPorts(system.membus) 44 cpu.clock = '2GHz' 45 46# connect memory to membus 47system.physmem.port = system.membus.port 48 |
49 50# ----------------------- 51# run simulation 52# ----------------------- 53 |
54root = Root(full_system = False, system = system) |
55root.system.mem_mode = 'timing' |