o3-timing-mp-ruby.py (11682:612f75cf36a0) | o3-timing-mp-ruby.py (13718:89e8bcc7253b) |
---|---|
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 16 unchanged lines hidden (view full) --- 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31 32nb_cores = 4 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 16 unchanged lines hidden (view full) --- 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31 32nb_cores = 4 |
33cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] | 33cpus = [ DerivO3CPU(cpu_id=i) for i in range(nb_cores) ] |
34 35import ruby_config 36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 37 38# system simulated 39system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(), 40 mem_mode = "timing", 41 clk_domain = SrcClockDomain(clock = '1GHz')) --- 24 unchanged lines hidden --- | 34 35import ruby_config 36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 37 38# system simulated 39system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(), 40 mem_mode = "timing", 41 clk_domain = SrcClockDomain(clock = '1GHz')) --- 24 unchanged lines hidden --- |