1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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34nb_cores = 4
35cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37import ruby_config
38ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
39
40# system simulated
41system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
42 mem_mode = "timing")
43system.clock = '1GHz'
44
45for cpu in cpus:
46 # create the interrupt controller
47 cpu.createInterruptController()
48 cpu.connectAllPorts(system.membus)
49 cpu.clock = '2GHz'
50
51# connect memory to membus
52system.physmem.port = system.membus.master
53
54# Connect the system port for loading of binaries etc
55system.system_port = system.membus.slave
56
57# -----------------------
58# run simulation
59# -----------------------
60
61root = Root(full_system = False, system = system)
62root.system.mem_mode = 'timing'