| o3-timing-checker.py (9728:7daeab1685e9) | o3-timing-checker.py (9790:ccc428657233) |
|---|---|
| 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 41 unchanged lines hidden (view full) --- 50# should set hit latency and response latency to 20 cycles as for 51# other scripts 52cpu.clock = '2GHz' 53 54system = System(cpu = cpu, 55 physmem = DDR3_1600_x64(), 56 membus = CoherentBus(), 57 mem_mode = "timing") | 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 41 unchanged lines hidden (view full) --- 50# should set hit latency and response latency to 20 cycles as for 51# other scripts 52cpu.clock = '2GHz' 53 54system = System(cpu = cpu, 55 physmem = DDR3_1600_x64(), 56 membus = CoherentBus(), 57 mem_mode = "timing") |
| 58system.clock = '1GHz' |
|
| 58system.system_port = system.membus.slave 59system.physmem.port = system.membus.master 60cpu.connectAllPorts(system.membus) 61 62root = Root(full_system = False, system = system) | 59system.system_port = system.membus.slave 60system.physmem.port = system.membus.master 61cpu.connectAllPorts(system.membus) 62 63root = Root(full_system = False, system = system) |