o3-timing-checker.py (9263:066099902102) o3-timing-checker.py (9288:3d6da8559605)
1# Copyright (c) 2011 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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37
38import m5
39from m5.objects import *
40m5.util.addToPath('../configs/common')
41
42class MyCache(BaseCache):
43 assoc = 2
44 block_size = 64
1# Copyright (c) 2011 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 28 unchanged lines hidden (view full) ---

37
38import m5
39from m5.objects import *
40m5.util.addToPath('../configs/common')
41
42class MyCache(BaseCache):
43 assoc = 2
44 block_size = 64
45 hit_latency = '1ns'
46 response_latency = '1ns'
45 hit_latency = 2
46 response_latency = 2
47 mshrs = 10
48 tgts_per_mshr = 5
49
50class MyL1Cache(MyCache):
51 is_top_level = True
52 tgts_per_mshr = 20
53
54cpu = DerivO3CPU(cpu_id=0)
55cpu.createInterruptController()
56cpu.addCheckerCpu()
57cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
58 MyL1Cache(size = '256kB'),
59 MyCache(size = '2MB'))
47 mshrs = 10
48 tgts_per_mshr = 5
49
50class MyL1Cache(MyCache):
51 is_top_level = True
52 tgts_per_mshr = 20
53
54cpu = DerivO3CPU(cpu_id=0)
55cpu.createInterruptController()
56cpu.addCheckerCpu()
57cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
58 MyL1Cache(size = '256kB'),
59 MyCache(size = '2MB'))
60# @todo Note that the L2 latency here is unmodified and 2 cycles,
61# should set hit latency and response latency to 20 cycles as for
62# other scripts
60cpu.clock = '2GHz'
61
62system = System(cpu = cpu,
63 physmem = SimpleMemory(),
64 membus = CoherentBus())
65system.system_port = system.membus.slave
66system.physmem.port = system.membus.master
67cpu.connectAllPorts(system.membus)
68
69root = Root(full_system = False, system = system)
63cpu.clock = '2GHz'
64
65system = System(cpu = cpu,
66 physmem = SimpleMemory(),
67 membus = CoherentBus())
68system.system_port = system.membus.slave
69system.physmem.port = system.membus.master
70cpu.connectAllPorts(system.membus)
71
72root = Root(full_system = False, system = system)