| o3-timing-checker.py (9036:6385cf85bf12) | o3-timing-checker.py (9263:066099902102) |
|---|---|
| 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 28 unchanged lines hidden (view full) --- 37 38import m5 39from m5.objects import * 40m5.util.addToPath('../configs/common') 41 42class MyCache(BaseCache): 43 assoc = 2 44 block_size = 64 | 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 28 unchanged lines hidden (view full) --- 37 38import m5 39from m5.objects import * 40m5.util.addToPath('../configs/common') 41 42class MyCache(BaseCache): 43 assoc = 2 44 block_size = 64 |
| 45 latency = '1ns' | 45 hit_latency = '1ns' 46 response_latency = '1ns' |
| 46 mshrs = 10 47 tgts_per_mshr = 5 48 49class MyL1Cache(MyCache): 50 is_top_level = True 51 tgts_per_mshr = 20 52 53cpu = DerivO3CPU(cpu_id=0) --- 15 unchanged lines hidden --- | 47 mshrs = 10 48 tgts_per_mshr = 5 49 50class MyL1Cache(MyCache): 51 is_top_level = True 52 tgts_per_mshr = 20 53 54cpu = DerivO3CPU(cpu_id=0) --- 15 unchanged lines hidden --- |