| o3-timing-checker.py (8931:7a1dfb191e3f) | o3-timing-checker.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 46 unchanged lines hidden (view full) --- 55cpu.addCheckerCpu() 56cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 57 MyL1Cache(size = '256kB'), 58 MyCache(size = '2MB')) 59cpu.clock = '2GHz' 60 61system = System(cpu = cpu, 62 physmem = SimpleMemory(), | 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 46 unchanged lines hidden (view full) --- 55cpu.addCheckerCpu() 56cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 57 MyL1Cache(size = '256kB'), 58 MyCache(size = '2MB')) 59cpu.clock = '2GHz' 60 61system = System(cpu = cpu, 62 physmem = SimpleMemory(), |
| 63 membus = Bus()) | 63 membus = CoherentBus()) |
| 64system.system_port = system.membus.slave 65system.physmem.port = system.membus.master 66cpu.connectAllPorts(system.membus) 67 68root = Root(full_system = False, system = system) | 64system.system_port = system.membus.slave 65system.physmem.port = system.membus.master 66cpu.connectAllPorts(system.membus) 67 68root = Root(full_system = False, system = system) |