memtest.py (9827:f47274776aa0) memtest.py (10405:7a618c07e663)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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32from Caches import *
33
34#MAX CORES IS 8 with the fals sharing method
35nb_cores = 8
36cpus = [ MemTest() for i in xrange(nb_cores) ]
37
38# system simulated
39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 23 unchanged lines hidden (view full) ---

32from Caches import *
33
34#MAX CORES IS 8 with the fals sharing method
35nb_cores = 8
36cpus = [ MemTest() for i in xrange(nb_cores) ]
37
38# system simulated
39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
40 funcbus = NoncoherentBus(),
40 funcbus = NoncoherentXBar(),
41 physmem = SimpleMemory(),
41 physmem = SimpleMemory(),
42 membus = CoherentBus(width=16))
42 membus = CoherentXBar(width=16))
43# Dummy voltage domain for all our clock domains
44system.voltage_domain = VoltageDomain()
45system.clk_domain = SrcClockDomain(clock = '1GHz',
46 voltage_domain = system.voltage_domain)
47
48# Create a seperate clock domain for components that should run at
49# CPUs frequency
50system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
51 voltage_domain = system.voltage_domain)
52
43# Dummy voltage domain for all our clock domains
44system.voltage_domain = VoltageDomain()
45system.clk_domain = SrcClockDomain(clock = '1GHz',
46 voltage_domain = system.voltage_domain)
47
48# Create a seperate clock domain for components that should run at
49# CPUs frequency
50system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
51 voltage_domain = system.voltage_domain)
52
53system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16)
53system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16)
54system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
55system.l2c.cpu_side = system.toL2Bus.master
56
57# connect l2c to membus
58system.l2c.mem_side = system.membus.slave
59
60# add L1 caches
61for cpu in cpus:

--- 25 unchanged lines hidden --- 		54system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
55system.l2c.cpu_side = system.toL2Bus.master
56
57# connect l2c to membus
58system.l2c.mem_side = system.membus.slave
59
60# add L1 caches
61for cpu in cpus:

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