| memtest.py (9793:6e6cefc1db1f) | memtest.py (9827:f47274776aa0) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest() for i in xrange(nb_cores) ] 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest() for i in xrange(nb_cores) ] 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(), |
| 42 membus = CoherentBus(width=16), 43 clk_domain = SrcClockDomain(clock = '1GHz')) | 42 membus = CoherentBus(width=16)) 43# Dummy voltage domain for all our clock domains 44system.voltage_domain = VoltageDomain() 45system.clk_domain = SrcClockDomain(clock = '1GHz', 46 voltage_domain = system.voltage_domain) |
| 44 45# Create a seperate clock domain for components that should run at 46# CPUs frequency | 47 48# Create a seperate clock domain for components that should run at 49# CPUs frequency |
| 47system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') | 50system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 51 voltage_domain = system.voltage_domain) |
| 48 49system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16) 50system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 51system.l2c.cpu_side = system.toL2Bus.master 52 53# connect l2c to membus 54system.l2c.mem_side = system.membus.slave 55 --- 27 unchanged lines hidden --- | 52 53system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16) 54system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 55system.l2c.cpu_side = system.toL2Bus.master 56 57# connect l2c to membus 58system.l2c.mem_side = system.membus.slave 59 --- 27 unchanged lines hidden --- |