| memtest.py (9790:ccc428657233) | memtest.py (9793:6e6cefc1db1f) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 19 unchanged lines hidden (view full) --- 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 19 unchanged lines hidden (view full) --- 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 |
| 36cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] | 36cpus = [ MemTest() for i in xrange(nb_cores) ] |
| 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(), | 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(), |
| 42 membus = CoherentBus(width=16)) 43system.clock = '1GHz' | 42 membus = CoherentBus(width=16), 43 clk_domain = SrcClockDomain(clock = '1GHz')) |
| 44 | 44 |
| 45# l2cache & bus 46system.toL2Bus = CoherentBus(clock="2GHz", width=16) 47system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) | 45# Create a seperate clock domain for components that should run at 46# CPUs frequency 47system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') 48 49system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16) 50system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) |
| 48system.l2c.cpu_side = system.toL2Bus.master 49 50# connect l2c to membus 51system.l2c.mem_side = system.membus.slave 52 53# add L1 caches 54for cpu in cpus: | 51system.l2c.cpu_side = system.toL2Bus.master 52 53# connect l2c to membus 54system.l2c.mem_side = system.membus.slave 55 56# add L1 caches 57for cpu in cpus: |
| 58 # All cpus are associated with cpu_clk_domain 59 cpu.clk_domain = system.cpu_clk_domain |
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| 55 cpu.l1c = L1Cache(size = '32kB', assoc = 4) 56 cpu.l1c.cpu_side = cpu.test 57 cpu.l1c.mem_side = system.toL2Bus.slave 58 system.funcbus.slave = cpu.functional 59 60system.system_port = system.membus.slave 61 62# connect reference memory to funcbus --- 15 unchanged lines hidden --- | 60 cpu.l1c = L1Cache(size = '32kB', assoc = 4) 61 cpu.l1c.cpu_side = cpu.test 62 cpu.l1c.mem_side = system.toL2Bus.slave 63 system.funcbus.slave = cpu.functional 64 65system.system_port = system.membus.slave 66 67# connect reference memory to funcbus --- 15 unchanged lines hidden --- |