| memtest.py (9321:7f0464326b2b) | memtest.py (9788:5558ee8dd7d9) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 25 unchanged lines hidden (view full) --- 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(), |
| 42 membus = CoherentBus(clock="1GHz", width=16)) | 42 membus = CoherentBus(width=16)) |
| 43 44# l2cache & bus 45system.toL2Bus = CoherentBus(clock="2GHz", width=16) 46system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) 47system.l2c.cpu_side = system.toL2Bus.master 48 49# connect l2c to membus 50system.l2c.mem_side = system.membus.slave --- 26 unchanged lines hidden --- | 43 44# l2cache & bus 45system.toL2Bus = CoherentBus(clock="2GHz", width=16) 46system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) 47system.l2c.cpu_side = system.toL2Bus.master 48 49# connect l2c to membus 50system.l2c.mem_side = system.membus.slave --- 26 unchanged lines hidden --- |