memtest.py (9288:3d6da8559605) memtest.py (9321:7f0464326b2b)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 14 unchanged lines hidden (view full) ---

23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
31
33
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37 hit_latency = 2
38 response_latency = 2
39 block_size = 64
40 mshrs = 12
41 tgts_per_mshr = 8
42 is_top_level = True
43
44# ----------------------
45# Base L2 Cache
46# ----------------------
47
48class L2(BaseCache):
49 block_size = 64
50 hit_latency = 20
51 response_latency = 20
52 mshrs = 92
53 tgts_per_mshr = 16
54 write_buffers = 8
55
56#MAX CORES IS 8 with the fals sharing method
57nb_cores = 8
58cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
59
60# system simulated
61system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
62 funcbus = NoncoherentBus(),
63 physmem = SimpleMemory(),
64 membus = CoherentBus(clock="1GHz", width=16))
65
66# l2cache & bus
67system.toL2Bus = CoherentBus(clock="2GHz", width=16)
34#MAX CORES IS 8 with the fals sharing method
35nb_cores = 8
36cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
37
38# system simulated
39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
40 funcbus = NoncoherentBus(),
41 physmem = SimpleMemory(),
42 membus = CoherentBus(clock="1GHz", width=16))
43
44# l2cache & bus
45system.toL2Bus = CoherentBus(clock="2GHz", width=16)
68system.l2c = L2(clock = '2GHz', size='64kB', assoc=8)
46system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8)
69system.l2c.cpu_side = system.toL2Bus.master
70
71# connect l2c to membus
72system.l2c.mem_side = system.membus.slave
73
74# add L1 caches
75for cpu in cpus:
47system.l2c.cpu_side = system.toL2Bus.master
48
49# connect l2c to membus
50system.l2c.mem_side = system.membus.slave
51
52# add L1 caches
53for cpu in cpus:
76 cpu.l1c = L1(size = '32kB', assoc = 4)
54 cpu.l1c = L1Cache(size = '32kB', assoc = 4)
77 cpu.l1c.cpu_side = cpu.test
78 cpu.l1c.mem_side = system.toL2Bus.slave
79 system.funcbus.slave = cpu.functional
80
81system.system_port = system.membus.slave
82
83# connect reference memory to funcbus
84system.funcmem.port = system.funcbus.master

--- 14 unchanged lines hidden --- 		55 cpu.l1c.cpu_side = cpu.test
56 cpu.l1c.mem_side = system.toL2Bus.slave
57 system.funcbus.slave = cpu.functional
58
59system.system_port = system.membus.slave
60
61# connect reference memory to funcbus
62system.funcmem.port = system.funcbus.master

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