| memtest.py (8931:7a1dfb191e3f) | memtest.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 44 unchanged lines hidden (view full) --- 53 54#MAX CORES IS 8 with the fals sharing method 55nb_cores = 8 56cpus = [ MemTest() for i in xrange(nb_cores) ] 57 58# system simulated 59system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 60 physmem = SimpleMemory(), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 44 unchanged lines hidden (view full) --- 53 54#MAX CORES IS 8 with the fals sharing method 55nb_cores = 8 56cpus = [ MemTest() for i in xrange(nb_cores) ] 57 58# system simulated 59system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 60 physmem = SimpleMemory(), |
| 61 membus = Bus(clock="500GHz", width=16)) | 61 membus = CoherentBus(clock="500GHz", width=16)) |
| 62 63# l2cache & bus | 62 63# l2cache & bus |
| 64system.toL2Bus = Bus(clock="500GHz", width=16) | 64system.toL2Bus = CoherentBus(clock="500GHz", width=16) |
| 65system.l2c = L2(size='64kB', assoc=8) 66system.l2c.cpu_side = system.toL2Bus.master 67 68# connect l2c to membus 69system.l2c.mem_side = system.membus.slave 70 71# add L1 caches 72for cpu in cpus: --- 20 unchanged lines hidden --- | 65system.l2c = L2(size='64kB', assoc=8) 66system.l2c.cpu_side = system.toL2Bus.master 67 68# connect l2c to membus 69system.l2c.mem_side = system.membus.slave 70 71# add L1 caches 72for cpu in cpus: --- 20 unchanged lines hidden --- |