memtest.py (8833:2870638642bd) | memtest.py (8839:eeb293859255) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 49 unchanged lines hidden (view full) --- 58# system simulated 59system = System(cpu = cpus, funcmem = PhysicalMemory(), 60 physmem = PhysicalMemory(), 61 membus = Bus(clock="500GHz", width=16)) 62 63# l2cache & bus 64system.toL2Bus = Bus(clock="500GHz", width=16) 65system.l2c = L2(size='64kB', assoc=8) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 49 unchanged lines hidden (view full) --- 58# system simulated 59system = System(cpu = cpus, funcmem = PhysicalMemory(), 60 physmem = PhysicalMemory(), 61 membus = Bus(clock="500GHz", width=16)) 62 63# l2cache & bus 64system.toL2Bus = Bus(clock="500GHz", width=16) 65system.l2c = L2(size='64kB', assoc=8) |
66system.l2c.cpu_side = system.toL2Bus.port | 66system.l2c.cpu_side = system.toL2Bus.master |
67 68# connect l2c to membus | 67 68# connect l2c to membus |
69system.l2c.mem_side = system.membus.port | 69system.l2c.mem_side = system.membus.slave |
70 71# add L1 caches 72for cpu in cpus: 73 cpu.l1c = L1(size = '32kB', assoc = 4) 74 cpu.l1c.cpu_side = cpu.test | 70 71# add L1 caches 72for cpu in cpus: 73 cpu.l1c = L1(size = '32kB', assoc = 4) 74 cpu.l1c.cpu_side = cpu.test |
75 cpu.l1c.mem_side = system.toL2Bus.port | 75 cpu.l1c.mem_side = system.toL2Bus.slave |
76 system.funcmem.port = cpu.functional 77 | 76 system.funcmem.port = cpu.functional 77 |
78system.system_port = system.membus.port | 78system.system_port = system.membus.slave |
79 80# connect memory to membus | 79 80# connect memory to membus |
81system.physmem.port = system.membus.port | 81system.physmem.port = system.membus.master |
82 83 84# ----------------------- 85# run simulation 86# ----------------------- 87 88root = Root( full_system = False, system = system ) 89root.system.mem_mode = 'timing' 90#root.trace.flags="Cache CachePort MemoryAccess" 91#root.trace.cycle=1 92 | 82 83 84# ----------------------- 85# run simulation 86# ----------------------- 87 88root = Root( full_system = False, system = system ) 89root.system.mem_mode = 'timing' 90#root.trace.flags="Cache CachePort MemoryAccess" 91#root.trace.cycle=1 92 |