memtest.py (8801:1a84c6a81299) memtest.py (8833:2870638642bd)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60 physmem = PhysicalMemory(),
61 membus = Bus(clock="500GHz", width=16))
62
63# l2cache & bus
64system.toL2Bus = Bus(clock="500GHz", width=16)
65system.l2c = L2(size='64kB', assoc=8)
66system.l2c.cpu_side = system.toL2Bus.port
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 50 unchanged lines hidden (view full) ---

59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60 physmem = PhysicalMemory(),
61 membus = Bus(clock="500GHz", width=16))
62
63# l2cache & bus
64system.toL2Bus = Bus(clock="500GHz", width=16)
65system.l2c = L2(size='64kB', assoc=8)
66system.l2c.cpu_side = system.toL2Bus.port
67system.l2c.num_cpus = nb_cores
68
69# connect l2c to membus
70system.l2c.mem_side = system.membus.port
71
72# add L1 caches
73for cpu in cpus:
74 cpu.l1c = L1(size = '32kB', assoc = 4)
75 cpu.l1c.cpu_side = cpu.test

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68# connect l2c to membus
69system.l2c.mem_side = system.membus.port
70
71# add L1 caches
72for cpu in cpus:
73 cpu.l1c = L1(size = '32kB', assoc = 4)
74 cpu.l1c.cpu_side = cpu.test

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