memtest.py (4876:a18cedc19da5) memtest.py (6978:ab05e20dc4a7)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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58system = System(cpu = cpus, funcmem = PhysicalMemory(),
59 physmem = PhysicalMemory(),
60 membus = Bus(clock="500GHz", width=16))
61
62# l2cache & bus
63system.toL2Bus = Bus(clock="500GHz", width=16)
64system.l2c = L2(size='64kB', assoc=8)
65system.l2c.cpu_side = system.toL2Bus.port
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 49 unchanged lines hidden (view full) ---

58system = System(cpu = cpus, funcmem = PhysicalMemory(),
59 physmem = PhysicalMemory(),
60 membus = Bus(clock="500GHz", width=16))
61
62# l2cache & bus
63system.toL2Bus = Bus(clock="500GHz", width=16)
64system.l2c = L2(size='64kB', assoc=8)
65system.l2c.cpu_side = system.toL2Bus.port
66system.l2c.num_cpus = nb_cores
66
67# connect l2c to membus
68system.l2c.mem_side = system.membus.port
69
70# add L1 caches
71for cpu in cpus:
72 cpu.l1c = L1(size = '32kB', assoc = 4)
73 cpu.l1c.cpu_side = cpu.test

--- 16 unchanged lines hidden --- 		67
68# connect l2c to membus
69system.l2c.mem_side = system.membus.port
70
71# add L1 caches
72for cpu in cpus:
73 cpu.l1c = L1(size = '32kB', assoc = 4)
74 cpu.l1c.cpu_side = cpu.test

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