memtest.py (3341:82c51d920701) memtest.py (4019:cdfb21ba304e)
1# Copyright (c) 2006 The Regents of The University of Michigan
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the

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48 block_size = 64
49 latency = 10
50 mshrs = 92
51 tgts_per_mshr = 16
52 write_buffers = 8
53
54#MAX CORES IS 8 with the fals sharing method
55nb_cores = 8
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the

--- 38 unchanged lines hidden (view full) ---

48 block_size = 64
49 latency = 10
50 mshrs = 92
51 tgts_per_mshr = 16
52 write_buffers = 8
53
54#MAX CORES IS 8 with the fals sharing method
55nb_cores = 8
56cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ]
56cpus = [ MemTest() for i in xrange(nb_cores) ]
57
58# system simulated
59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60 physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
61
62# l2cache & bus
63system.toL2Bus = Bus(clock="500GHz", width=16)
64system.l2c = L2(size='64kB', assoc=8)

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58# system simulated
59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60 physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
61
62# l2cache & bus
63system.toL2Bus = Bus(clock="500GHz", width=16)
64system.l2c = L2(size='64kB', assoc=8)

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