| memtest.py (3208:97d9cc1e626f) | memtest.py (3257:269df2f3bb2b) |
|---|---|
| 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 39 unchanged lines hidden (view full) --- 48 block_size = 64 49 latency = 10 50 mshrs = 92 51 tgts_per_mshr = 16 52 write_buffers = 8 53 54#MAX CORES IS 8 with the fals sharing method 55nb_cores = 8 | 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 39 unchanged lines hidden (view full) --- 48 block_size = 64 49 latency = 10 50 mshrs = 92 51 tgts_per_mshr = 16 52 write_buffers = 8 53 54#MAX CORES IS 8 with the fals sharing method 55nb_cores = 8 |
| 56cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0) for i in xrange(nb_cores) ] | 56cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ] |
| 57 58# system simulated 59system = System(cpu = cpus, funcmem = PhysicalMemory(), | 57 58# system simulated 59system = System(cpu = cpus, funcmem = PhysicalMemory(), |
| 60 physmem = PhysicalMemory(), membus = Bus()) | 60 physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16)) |
| 61 62# l2cache & bus | 61 62# l2cache & bus |
| 63system.toL2Bus = Bus() | 63system.toL2Bus = Bus(clock="500GHz", width=16) |
| 64system.l2c = L2(size='64kB', assoc=8) 65system.l2c.cpu_side = system.toL2Bus.port 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.port 69 70which_port = 0 71# add L1 caches --- 13 unchanged lines hidden (view full) --- 85 86 87# ----------------------- 88# run simulation 89# ----------------------- 90 91root = Root( system = system ) 92root.system.mem_mode = 'timing' | 64system.l2c = L2(size='64kB', assoc=8) 65system.l2c.cpu_side = system.toL2Bus.port 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.port 69 70which_port = 0 71# add L1 caches --- 13 unchanged lines hidden (view full) --- 85 86 87# ----------------------- 88# run simulation 89# ----------------------- 90 91root = Root( system = system ) 92root.system.mem_mode = 'timing' |
| 93root.trace.flags="Cache" | 93#root.trace.flags="Cache CachePort Bus" 94#root.trace.cycle=3810800 95 |