memtest.py (3196:8eb90bc29df8) memtest.py (3208:97d9cc1e626f)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37 latency = 1
38 block_size = 64
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37 latency = 1
38 block_size = 64
39 mshrs = 4
39 mshrs = 12
40 tgts_per_mshr = 8
41 protocol = CoherenceProtocol(protocol='moesi')
42
43# ----------------------
44# Base L2 Cache
45# ----------------------
46
47class L2(BaseCache):
48 block_size = 64
40 tgts_per_mshr = 8
41 protocol = CoherenceProtocol(protocol='moesi')
42
43# ----------------------
44# Base L2 Cache
45# ----------------------
46
47class L2(BaseCache):
48 block_size = 64
49 latency = 100
49 latency = 10
50 mshrs = 92
51 tgts_per_mshr = 16
52 write_buffers = 8
53
54#MAX CORES IS 8 with the fals sharing method
55nb_cores = 8
50 mshrs = 92
51 tgts_per_mshr = 16
52 write_buffers = 8
53
54#MAX CORES IS 8 with the fals sharing method
55nb_cores = 8
56cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
56cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0) for i in xrange(nb_cores) ]
57
58# system simulated
59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60 physmem = PhysicalMemory(), membus = Bus())
61
62# l2cache & bus
63system.toL2Bus = Bus()
57
58# system simulated
59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60 physmem = PhysicalMemory(), membus = Bus())
61
62# l2cache & bus
63system.toL2Bus = Bus()
64system.l2c = L2(size='4MB', assoc=8)
64system.l2c = L2(size='64kB', assoc=8)
65system.l2c.cpu_side = system.toL2Bus.port
66
67# connect l2c to membus
68system.l2c.mem_side = system.membus.port
69
70which_port = 0
71# add L1 caches
72for cpu in cpus:

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85
86
87# -----------------------
88# run simulation
89# -----------------------
90
91root = Root( system = system )
92root.system.mem_mode = 'timing'
65system.l2c.cpu_side = system.toL2Bus.port
66
67# connect l2c to membus
68system.l2c.mem_side = system.membus.port
69
70which_port = 0
71# add L1 caches
72for cpu in cpus:

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85
86
87# -----------------------
88# run simulation
89# -----------------------
90
91root = Root( system = system )
92root.system.mem_mode = 'timing'
93#root.trace.flags="InstExec"
94root.trace.flags="Bus"
93root.trace.flags="Cache"