memtest.py (3187:7eefad0aed11) memtest.py (3196:8eb90bc29df8)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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46
47class L2(BaseCache):
48 block_size = 64
49 latency = 100
50 mshrs = 92
51 tgts_per_mshr = 16
52 write_buffers = 8
53
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 37 unchanged lines hidden (view full) ---

46
47class L2(BaseCache):
48 block_size = 64
49 latency = 100
50 mshrs = 92
51 tgts_per_mshr = 16
52 write_buffers = 8
53
54nb_cores = 1
54#MAX CORES IS 8 with the fals sharing method
55nb_cores = 8
55cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
56
57# system simulated
58system = System(cpu = cpus, funcmem = PhysicalMemory(),
59 physmem = PhysicalMemory(), membus = Bus())
60
61# l2cache & bus
62system.toL2Bus = Bus()
63system.l2c = L2(size='4MB', assoc=8)
64system.l2c.cpu_side = system.toL2Bus.port
65
66# connect l2c to membus
67system.l2c.mem_side = system.membus.port
68
56cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
57
58# system simulated
59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60 physmem = PhysicalMemory(), membus = Bus())
61
62# l2cache & bus
63system.toL2Bus = Bus()
64system.l2c = L2(size='4MB', assoc=8)
65system.l2c.cpu_side = system.toL2Bus.port
66
67# connect l2c to membus
68system.l2c.mem_side = system.membus.port
69
70which_port = 0
69# add L1 caches
70for cpu in cpus:
71 cpu.l1c = L1(size = '32kB', assoc = 4)
72 cpu.l1c.cpu_side = cpu.test
73 cpu.l1c.mem_side = system.toL2Bus.port
71# add L1 caches
72for cpu in cpus:
73 cpu.l1c = L1(size = '32kB', assoc = 4)
74 cpu.l1c.cpu_side = cpu.test
75 cpu.l1c.mem_side = system.toL2Bus.port
74 system.funcmem.port = cpu.functional
76 if which_port == 0:
77 system.funcmem.port = cpu.functional
78 which_port = 1
79 else:
80 system.funcmem.functional = cpu.functional
75
76
77# connect memory to membus
78system.physmem.port = system.membus.port
79
80
81# -----------------------
82# run simulation
83# -----------------------
84
85root = Root( system = system )
86root.system.mem_mode = 'timing'
87#root.trace.flags="InstExec"
88root.trace.flags="Bus"
81
82
83# connect memory to membus
84system.physmem.port = system.membus.port
85
86
87# -----------------------
88# run simulation
89# -----------------------
90
91root = Root( system = system )
92root.system.mem_mode = 'timing'
93#root.trace.flags="InstExec"
94root.trace.flags="Bus"