| memtest.py (10405:7a618c07e663) | memtest.py (10688:22452667fd5c) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest() for i in xrange(nb_cores) ] 37 38# system simulated | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest() for i in xrange(nb_cores) ] 37 38# system simulated |
| 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentXBar(), | 39system = System(cpu = cpus, |
| 41 physmem = SimpleMemory(), 42 membus = CoherentXBar(width=16)) 43# Dummy voltage domain for all our clock domains 44system.voltage_domain = VoltageDomain() 45system.clk_domain = SrcClockDomain(clock = '1GHz', 46 voltage_domain = system.voltage_domain) 47 48# Create a seperate clock domain for components that should run at --- 8 unchanged lines hidden (view full) --- 57# connect l2c to membus 58system.l2c.mem_side = system.membus.slave 59 60# add L1 caches 61for cpu in cpus: 62 # All cpus are associated with cpu_clk_domain 63 cpu.clk_domain = system.cpu_clk_domain 64 cpu.l1c = L1Cache(size = '32kB', assoc = 4) | 40 physmem = SimpleMemory(), 41 membus = CoherentXBar(width=16)) 42# Dummy voltage domain for all our clock domains 43system.voltage_domain = VoltageDomain() 44system.clk_domain = SrcClockDomain(clock = '1GHz', 45 voltage_domain = system.voltage_domain) 46 47# Create a seperate clock domain for components that should run at --- 8 unchanged lines hidden (view full) --- 56# connect l2c to membus 57system.l2c.mem_side = system.membus.slave 58 59# add L1 caches 60for cpu in cpus: 61 # All cpus are associated with cpu_clk_domain 62 cpu.clk_domain = system.cpu_clk_domain 63 cpu.l1c = L1Cache(size = '32kB', assoc = 4) |
| 65 cpu.l1c.cpu_side = cpu.test | 64 cpu.l1c.cpu_side = cpu.port |
| 66 cpu.l1c.mem_side = system.toL2Bus.slave | 65 cpu.l1c.mem_side = system.toL2Bus.slave |
| 67 system.funcbus.slave = cpu.functional | |
| 68 69system.system_port = system.membus.slave 70 | 66 67system.system_port = system.membus.slave 68 |
| 71# connect reference memory to funcbus 72system.funcmem.port = system.funcbus.master 73 | |
| 74# connect memory to membus 75system.physmem.port = system.membus.master 76 77 78# ----------------------- 79# run simulation 80# ----------------------- 81 82root = Root( full_system = False, system = system ) 83root.system.mem_mode = 'timing' | 69# connect memory to membus 70system.physmem.port = system.membus.master 71 72 73# ----------------------- 74# run simulation 75# ----------------------- 76 77root = Root( full_system = False, system = system ) 78root.system.mem_mode = 'timing' |
| 84#root.trace.flags="Cache CachePort MemoryAccess" 85#root.trace.cycle=1 | |
| 86 | 79 |