1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31 32# -------------------- 33# Base L1 Cache 34# ==================== 35 36class L1(BaseCache):
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37 hit_latency = '1ns'
38 response_latency = '1ns'
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37 hit_latency = 2 38 response_latency = 2 |
39 block_size = 64 40 mshrs = 12 41 tgts_per_mshr = 8 42 is_top_level = True 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64
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50 hit_latency = '10ns'
51 response_latency = '10ns'
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50 hit_latency = 20 51 response_latency = 20 |
52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56#MAX CORES IS 8 with the fals sharing method 57nb_cores = 8 58cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] 59 60# system simulated 61system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 62 funcbus = NoncoherentBus(), 63 physmem = SimpleMemory(), 64 membus = CoherentBus(clock="1GHz", width=16)) 65 66# l2cache & bus 67system.toL2Bus = CoherentBus(clock="2GHz", width=16)
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68system.l2c = L2(size='64kB', assoc=8)
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68system.l2c = L2(clock = '2GHz', size='64kB', assoc=8) |
69system.l2c.cpu_side = system.toL2Bus.master 70 71# connect l2c to membus 72system.l2c.mem_side = system.membus.slave 73 74# add L1 caches 75for cpu in cpus: 76 cpu.l1c = L1(size = '32kB', assoc = 4) 77 cpu.l1c.cpu_side = cpu.test 78 cpu.l1c.mem_side = system.toL2Bus.slave 79 system.funcbus.slave = cpu.functional 80 81system.system_port = system.membus.slave 82 83# connect reference memory to funcbus 84system.funcmem.port = system.funcbus.master 85 86# connect memory to membus 87system.physmem.port = system.membus.master 88 89 90# ----------------------- 91# run simulation 92# ----------------------- 93 94root = Root( full_system = False, system = system ) 95root.system.mem_mode = 'timing' 96#root.trace.flags="Cache CachePort MemoryAccess" 97#root.trace.cycle=1 98
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