1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 41 unchanged lines hidden (view full) --- 50 hit_latency = '10ns' 51 response_latency = '10ns' 52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56#MAX CORES IS 8 with the fals sharing method 57nb_cores = 8 |
58cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] |
59 60# system simulated 61system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 62 funcbus = NoncoherentBus(), 63 physmem = SimpleMemory(), |
64 membus = CoherentBus(clock="1GHz", width=16)) |
65 66# l2cache & bus |
67system.toL2Bus = CoherentBus(clock="2GHz", width=16) |
68system.l2c = L2(size='64kB', assoc=8) 69system.l2c.cpu_side = system.toL2Bus.master 70 71# connect l2c to membus 72system.l2c.mem_side = system.membus.slave 73 74# add L1 caches 75for cpu in cpus: --- 23 unchanged lines hidden --- |