1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 43 unchanged lines hidden (view full) --- 52 write_buffers = 8 53 54#MAX CORES IS 8 with the fals sharing method 55nb_cores = 8 56cpus = [ MemTest() for i in xrange(nb_cores) ] 57 58# system simulated 59system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), |
60 funcbus = NoncoherentBus(), |
61 physmem = SimpleMemory(), 62 membus = CoherentBus(clock="500GHz", width=16)) 63 64# l2cache & bus 65system.toL2Bus = CoherentBus(clock="500GHz", width=16) 66system.l2c = L2(size='64kB', assoc=8) 67system.l2c.cpu_side = system.toL2Bus.master 68 69# connect l2c to membus 70system.l2c.mem_side = system.membus.slave 71 72# add L1 caches 73for cpu in cpus: 74 cpu.l1c = L1(size = '32kB', assoc = 4) 75 cpu.l1c.cpu_side = cpu.test 76 cpu.l1c.mem_side = system.toL2Bus.slave |
77 system.funcbus.slave = cpu.functional |
78 79system.system_port = system.membus.slave 80 |
81# connect reference memory to funcbus 82system.funcmem.port = system.funcbus.master 83 |
84# connect memory to membus 85system.physmem.port = system.membus.master 86 87 88# ----------------------- 89# run simulation 90# ----------------------- 91 92root = Root( full_system = False, system = system ) 93root.system.mem_mode = 'timing' 94#root.trace.flags="Cache CachePort MemoryAccess" 95#root.trace.cycle=1 96 |