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< cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
---
> cpus = [ MemTest() for i in xrange(nb_cores) ]
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< membus = CoherentBus(width=16))
< system.clock = '1GHz'
---
> membus = CoherentBus(width=16),
> clk_domain = SrcClockDomain(clock = '1GHz'))
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< # l2cache & bus
< system.toL2Bus = CoherentBus(clock="2GHz", width=16)
< system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8)
---
> # Create a seperate clock domain for components that should run at
> # CPUs frequency
> system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
>
> system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16)
> system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
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> # All cpus are associated with cpu_clk_domain
> cpu.clk_domain = system.cpu_clk_domain