39,40c39
< system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
< funcbus = NoncoherentXBar(),
---
> system = System(cpu = cpus,
65c64
< cpu.l1c.cpu_side = cpu.test
---
> cpu.l1c.cpu_side = cpu.port
67d65
< system.funcbus.slave = cpu.functional
71,73d68
< # connect reference memory to funcbus
< system.funcmem.port = system.funcbus.master
<
84,85d78
< #root.trace.flags="Cache CachePort MemoryAccess"
< #root.trace.cycle=1