1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8
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36cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
| 36cpus = [ MemTest() for i in xrange(nb_cores) ]
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37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(),
| 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(),
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42 membus = CoherentBus(width=16)) 43system.clock = '1GHz'
| 42 membus = CoherentBus(width=16), 43 clk_domain = SrcClockDomain(clock = '1GHz'))
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44
| 44
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45# l2cache & bus 46system.toL2Bus = CoherentBus(clock="2GHz", width=16) 47system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8)
| 45# Create a seperate clock domain for components that should run at 46# CPUs frequency 47system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') 48 49system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16) 50system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
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48system.l2c.cpu_side = system.toL2Bus.master 49 50# connect l2c to membus 51system.l2c.mem_side = system.membus.slave 52 53# add L1 caches 54for cpu in cpus:
| 51system.l2c.cpu_side = system.toL2Bus.master 52 53# connect l2c to membus 54system.l2c.mem_side = system.membus.slave 55 56# add L1 caches 57for cpu in cpus:
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| 58 # All cpus are associated with cpu_clk_domain 59 cpu.clk_domain = system.cpu_clk_domain
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55 cpu.l1c = L1Cache(size = '32kB', assoc = 4) 56 cpu.l1c.cpu_side = cpu.test 57 cpu.l1c.mem_side = system.toL2Bus.slave 58 system.funcbus.slave = cpu.functional 59 60system.system_port = system.membus.slave 61 62# connect reference memory to funcbus 63system.funcmem.port = system.funcbus.master 64 65# connect memory to membus 66system.physmem.port = system.membus.master 67 68 69# ----------------------- 70# run simulation 71# ----------------------- 72 73root = Root( full_system = False, system = system ) 74root.system.mem_mode = 'timing' 75#root.trace.flags="Cache CachePort MemoryAccess" 76#root.trace.cycle=1 77
| 60 cpu.l1c = L1Cache(size = '32kB', assoc = 4) 61 cpu.l1c.cpu_side = cpu.test 62 cpu.l1c.mem_side = system.toL2Bus.slave 63 system.funcbus.slave = cpu.functional 64 65system.system_port = system.membus.slave 66 67# connect reference memory to funcbus 68system.funcmem.port = system.funcbus.master 69 70# connect memory to membus 71system.physmem.port = system.membus.master 72 73 74# ----------------------- 75# run simulation 76# ----------------------- 77 78root = Root( full_system = False, system = system ) 79root.system.mem_mode = 'timing' 80#root.trace.flags="Cache CachePort MemoryAccess" 81#root.trace.cycle=1 82
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