memtest.py (8706:b1838faf3bcc) | memtest.py (8801:1a84c6a81299) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 72 unchanged lines hidden (view full) --- 81# connect memory to membus 82system.physmem.port = system.membus.port 83 84 85# ----------------------- 86# run simulation 87# ----------------------- 88 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 72 unchanged lines hidden (view full) --- 81# connect memory to membus 82system.physmem.port = system.membus.port 83 84 85# ----------------------- 86# run simulation 87# ----------------------- 88 |
89root = Root( system = system ) | 89root = Root( full_system = False, system = system ) |
90root.system.mem_mode = 'timing' 91#root.trace.flags="Cache CachePort MemoryAccess" 92#root.trace.cycle=1 93 | 90root.system.mem_mode = 'timing' 91#root.trace.flags="Cache CachePort MemoryAccess" 92#root.trace.cycle=1 93 |